Scalability prediction of the sparse matrix-vector multiplication using the interconnection network simulator

Abstract

A 4D-torus high-speed interconnect for supercomputers is being developed at JSC NICEVT. The router ASIC is to be issued by the end of 2012. This article analyzes two variants of sparse matrix-vector multiplication (SpMV) implementation. For each case theoretical communication estimate is given. Both algorithms are implemented using MPI+OpenMP, also an implementation for the interconnection network simulator is considered. Results on the simulator  configured to correspond to the multidimensional torus interconnect being developed at JSC NICEVT show better SpMV scalability compared with performance results of Lomonosov supercomputer at RCC MSU and BlueGene/P at CMC MSU. Sustained SpMV performance for the simulator is 346 GFlops on 2048 computational nodes, for Lomonosov – 11.6 Gflops on 256 nodes and 8.3 GFlops for BlueGene/P on 1024 nodes. To confirm the simulator results adequacy the prototype cluster consisting of 9 nodes was simulated. The results for various parameters showed an average deviation of 13% and maximum deviation of 32%.